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| LEADER |
00668nam a2200181 a 4500 |
| 001 |
1532940 |
| 005 |
20171111233623.0 |
| 008 |
060123s2006 cy da r 000 u eng d |
| 020 |
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|a 0387244115
|q hbk.
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| 040 |
|
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|a CY
|b University of Cyprus
|e AACR2
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| 050 |
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|a TK7874.58.B47 2006
|
| 100 |
1 |
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|a Bertacco, Valeria
|
| 245 |
1 |
0 |
|a Scalable hardware verification with symbolic simulation/
|c Valeria Bertacco
|
| 260 |
|
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|a New York:
|b Springer,
|c c2006
|
| 300 |
|
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|a xx, 180 p. :
|b ill. ;
|c 24 cm.
|
| 504 |
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|a Includes bibliographical references and index.
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| 650 |
|
0 |
|a Integrated circuits
|x Verification
|
| 952 |
|
|
|a CY-NiOUC
|b 5a042e856c5ad14ac1e88888
|c 998a
|d 945l
|e TK7874.58.B47 2006
|t 1
|x m
|z Books
|
