Table of Contents: Logic synthesis and optimization/

Other Authors:	Sasao, Tsutomu,
Format:	Book
Language:	English
Published:	Boston: Kluwer Academic Publishers, c1993,
Series:	The Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing
Subjects:	Logic circuits > Design and construction > Data processing Logic design > Data processing

Table of Contents:

1. A New Exact Minimizer for Two-Level Logic Synthesis / R. K. Brayton, P. C. McGeer, J. V. Sanghavi and A. L. Sangiovanni-Vincentelli
2. A New Graph Based Prime Computation Technique / O. Coudert and J. C. Madre
3. Logic Synthesizers, the Transduction Method and Its Extension, Sylon / S. Muroga
4. Network Optimization Using Don't-Cares and Boolean Relations / K-C. Chen and M. Fujita
5. Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning / M. Fujita, Y. Matsunaga, Y. Tamiya and K-C. Chen
6. A Partitioning Method for Area Optimization by Tree Analysis / Y. Nakamura, K. Wakabayashi and T. Fujita
7. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams / S-W. Jeong and F. Somenzi
8. Delay Models and Exact Timing Analysis / P. C. McGeer, A. Saldanha, R. K. Brayton and A. L. Sangiovanni-Vincentelli
9. Challenges to Dependable Asynchronous Processor Design / T. Nanya
10. Efficient Spectral Techniques for Logic Synthesis / D. Varma and E. A. Trachtenberg
11. FPGA Design by Generalized Functional Decomposition / T. Sasao
12. Logic Synthesis With Exor Gates / T. Sasao
13. AND-EXOR Expressions and Their Optimization / T. Sasao
14. A Generation Method for Exor-Sum-Of-Products Expressions Using Shared Binary Decision Diagrams / K. Yasuoka
15. A New Technology Mapping Method Based on Concurrent Factorization and Mapping / M. Inamori and A. Takahara
16. Gate Sizing for Cell-Based Designs / W-P. Lee and Y-L. Lin.