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01002nam a2200229 a 4500 |
| 001 |
1508825 |
| 005 |
20171111233604.0 |
| 008 |
050214s2001 cy da r 000 u eng d |
| 020 |
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|a 0792373685
|q hbk.
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| 040 |
|
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|a CY
|b University of Cyprus
|e AACR2
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| 050 |
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|a TK7874.75.B47 2001
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| 100 |
1 |
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|a Bening, Lionel,
|d 1939-
|
| 245 |
1 |
0 |
|a Principles of verifiable RTL design:
|b a functional coding style supporting verification processes in Verilog/
|c Lionel Bening and Harry Foster
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| 250 |
|
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|a 2nd ed.
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| 260 |
|
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|a Boston:
|b Kluwer Academic Publishers,
|c c2001
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| 300 |
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|a xxiii, 281 p. :
|b ill. ;
|c 25 cm.
|
| 504 |
|
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|a Includes bibliographical references (p. [247]-254) and index.
|
| 650 |
|
0 |
|a Integrated circuits
|x Very large scale integration
|x Computer-aided design
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| 650 |
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0 |
|a Verilog (Computer hardware description language)
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| 650 |
|
0 |
|a Electronic digital computers
|x Computer-aided design
|
| 700 |
1 |
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|a Foster, Harry,
|
| 952 |
|
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|a CY-NiOUC
|b 5a042aed6c5ad14ac1e822d5
|c 998a
|d 945l
|e TK7874.75.B47 2001
|t 1
|x m
|z Books
|
